Multi-chip stacked packages have become the major technology for miniature of electronic devices to achieve system integration with large capacity. Since multiple chips are assembled in a single package, the footprint and volume of the single package is much smaller than the total of the footprints and volumes of packages which are individually assembled. Multi-chip stacked packages have the advantages of higher efficiency and multiple functions to meet the miniature requirements.
In the existing semiconductor industries, an interposer is needed to assemble a multi-chip stacked package with chips of different dimensions to complete electrical connections between a daughter chip and a mother chip where the interposer has the redistribution function to overcome different electrical connections between stacked chips with different dimensions, to avoid long bonding wire issues, and to make the impossible electrical connections become possible. Generally speaking, the interposer can be chosen from dummy chip, ceramic substrate, or organic substrate, however, reliability issues and uncontrollable package warpage after multi-chip stacking become major concerns where the reliability issue is caused by delamination due to CTE mismatch and due to poor adhesion between adjacent layers in a conventional stacked package.
As shown in FIG. 1, a conventional semiconductor packaging method using an interposer is disclosed. The process includes the following steps, “providing a mother chip” as step 11, “disposing the mother chip on a substrate” as step 12, “disposing an interposer onto the mother chip” as step 13, “disposing a daughter chip on the interposer” as step 14, “electrically connecting the daughter chip and the substrate through the interposer” as step 15, and “encapsulating the mother chip, the daughter chip, and the interposer” as step 16. A conventional semiconductor package using an interposer are shown in FIG. 2 and FIG. 3, primarily comprising a mother chip 110, a substrate 120, a daughter chip 130 which is smaller than the mother chip 110, and an interposer 170 disposed between the mother chip 110 and the daughter chip 130. The mother chip 110 is a large-sized chip for carrying the interposer 170 and the daughter chip 130. The semiconductor package is fabricated according to FIG. 1. In step 11, the mother chip 110 is provided where a plurality of electrodes 114 such as bonding pads are disposed on the active surface 113 of the mother chip 110. In step 12, the mother chip 110 is disposed on the substrate 120 by the existing die-attaching technology. In step 13, the interposer 170 is disposed on the active surface 113 of the mother chip 110 without covering the electrodes 114 where the interposer 170 has a redistribution layer 171 as shown in FIG. 3. In step 14, the back surface of the daughter chip 130 with a smaller dimension is attached to the interposer 170 where the daughter chip 130 has a plurality of bonding pads 132 on its active surface 131. Therefore, in this multi-chip stacked package with chips of different dimensions, the overall package thickness is increased by adding the interposer 170 with two die-attaching layers disposed on the top and bottom surfaces of the interposer 170. Moreover, in step 15, the interposer 170 is electrically connected to the substrate 120 by a plurality of electrically connecting components such as first bonding wires 141. The daughter chip 130 is electrically connected to the interposer 170 by a plurality of second bonding wires 142 connecting the bonding pads 132 and the redistribution layer 171. The interposer 170 is further electrically connected with the mother chip 110 by a plurality of third bonding wires 143 connecting the bonding pads 114 and the redistribution layer 171. Furthermore, in step 16, an encapsulant 150 is formed on the substrate 120, as shown in FIG. 3, to encapsulate the mother chip 110, the daughter chip 130, and the interposer 170. Since an interposer is a required component in the conventional multi-chip stacked package with chips of different dimensions so that the overall package thickness is increased and issues of delamination and warpage due to CTE mismatch and poor adhesion between adjacent layers are encountered.